The transistor is a commonly used element in integrated circuits. However, with the development of semiconductor process towards deep sub-micrometer scale or even nanometer scale, some new problems occurs. For example, the effect of parasitic capacitance on the performance of the transistor becomes more serious. In particular, the parasitic capacitance between a gate stack and an electric contact due to the height of the gate stack has become a huge obstacle for improving the performance of a nanometer scale transistor. In addition, due to a smaller gate-gate pitch, the height of the gate stack further brings about limitations to a plurality of process modules for manufacturing a semiconductor device.
Therefore, for improving the performance of the transistor, it is desirable to reduce the height of the gate stack. However, in the existing transistor, the adjustment of the threshold voltage of the transistor mainly depends on the work function of the gate stack, whereas the work function is affected by the material and height of the gate stack. Furthermore, in the process flow for manufacturing a transistor, the gate stack needs to have a certain height under some circumstances sequentially to function as a barrier layer. These factors all limit the reduction of the height of the gate stack.